The invention relates to microcomputers.
Single chip microcomputers are known including external communication ports so that the chip may be connected in a network, including for example connection to a host microcomputer for use in debugging routines. Such systems are also known in which each of the interconnected microcomputer chips has its own local memory. For speed of communication on on-chips it is common for bit packets to be transmitted between modules on a chip in a bit parallel format. However problems arise in both power consumption and available pin space in providing for external off-chip communications in the same parallel bit format as that used on-chip. Such microcomputers require access to instruction or code sequences and for efficient operation it is desirable for the instructions to be retrievable from locations within the address space of the CPU. One approach described in co-pending European patent application number 97308517.8 is to provide an on-chip external communication port forming part of the memory address space of the CPU from which instructions may be fetched and which translates between a parallel format on-chip and a less parallel format for off-chip communications.
In debugging it is often useful to be able to monitor program flow and take action when certain instructions are executed. However, in a conventional microprocessor this is difficult to implement. One solution is to implement the monitoring in software that is run by the CPU under testxe2x80x94this slows the CPU down and can invalidate the debugging process. Another solution is to watch for accessing of certain memory locations where instructions are stored. However, this does not permit watching for all instructions of a certain type wherever they are stored.
According to a first aspect of the present invention there is provided a computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.
According to a second aspect of the present invention there is provided a method of operating a computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; the method comprising comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.
Preferably the CPU includes a filter register for storing an instruction filter code which defines portions of the instructions and the instruction comparison code that are to be compared.
Preferably the watch comparator includes a first instruction filter for filtering the instructions passed on the data link with the instruction filter code to determine the portions of the instructions that are to be compared with the instruction comparison code. Suitably, the first instruction filter performs bitwise AND operations on the instructions and the instruction filter code.
The watch comparator suitably includes a second instruction filter for filtering the instruction comparison code with the instruction filter code to determine the portion of the instruction comparison code that is to be compared with the instructions. Suitably the second instruction filter performs bitwise AND operations on the instruction comparison code and the instruction filter code.
The portions of the instructions defined by the instruction filter code suitably specify operations to be performed by the data processing unit. The portion of the instruction comparison code defined by the instruction filter code may suitably specify a memory read operation. The portion of the instruction comparison code defined by the instruction filter code may suitably specify a memory write operation. The portion of the instruction comparison code defined by the instruction filter code may suitably specify data to be processed by the data processing unit. The portion of the instruction comparison code defined by the instruction filter code may suitably specify memory locations to be accessed by the CPU.
Preferably the memory is capable of storing more than one sequence of instructions for execution by the data processing unit. The CPU suitably includes a sequence register for storing data indicating which of the sequences of instructions is being executed by the data processing unit. The CPU suitably includes a sequence filter register for defining one of the sequences of instructions, and the watch comparator includes a sequence filter for suppressing the comparison output signal if the sequence defined by the sequence filter register is not the same as the sequence indicated by the sequence register.
The said method suitably includes a first filtering step of filtering the instructions passed on the data link with the instruction filter code to determine the portions of the instructions that are to be compared with the instruction comparison code.
The said first filtering step comprises performing bitwise AND operations on the instructions and the instruction filter code. Preferably the method includes a second filtering step of filtering the instruction comparison code with the instruction filter code to determine the portion of the instruction comparison code that is to be compared with the instructions. The second filtering step may comprise performing bitwise AND operations on the instruction comparison code and the instruction filter code.